--- iasm.dd	2009-07-15 09:23:59.047780900 -0600
+++ iasm-new.dd	2009-07-15 09:09:24.134780900 -0600
@@ -1,6 +1,6 @@
 Ddoc
 
-$(SPEC_S D x86 Inline Assembler,
+$(SPEC_S Inline Assembler,
 
 	<a href="http://www.digitalmars.com/gift/index.html" title="Gift Shop" target="_top">
 	<img src="d5.gif" border=0 align=right alt="Some Assembly Required" width=284 height=186>
@@ -8,7 +8,7 @@
 
 	$(P D, being a systems programming language, provides an inline
 	assembler.
-	The inline assembler is standardized for D implementations across
+	The base inline assembler is standardized for D implementations across
 	the same CPU family, for example, the Intel Pentium inline assembler
 	for a Win32 D compiler will be syntax compatible with the inline
 	assembler for Linux running on an Intel Pentium.
@@ -16,11 +16,17 @@
 
 	$(P Differing D implementations, however, are free to innovate upon
 	the memory model, function call/return conventions, argument
-	passing conventions, etc.
+	passing conventions, etc. They are also welcome to support newer opcodes
+	that have not been explicitly defined here as of yet, provided that they
+	maintain the standardized syntax and grammar outlined below. However, it
+	would be appreciated if the issue of missing or new opcodes are raised
+	through an enhancement request with Bugzilla.
 	)
 
-	$(P This document describes the x86 implementation of the inline
-	assembler.
+	$(P This document describes the $(B x86) and $(B x86-64) implementations of
+	the inline assembler. The inline assembler platform support that a compiler
+	provides is indicated by the $(B D_InlineAsm_X86) and
+	$(B D_InlineAsm_X86_64) version identifiers, respectively.
 	)
 
 $(GRAMMAR
@@ -122,12 +128,14 @@
 
 <h2>Opcodes</h2>
 
-	A list of supported opcodes is at the end.
+	A list of supported opcodes for each architecture is located at the end.
 	<p>
 
 	The following registers are supported. Register names
 	are always in upper case.
 
+<h3>x86</h3>
+	
 	<dl><dl>
 	<dt>$(B AL), $(B AH), $(B AX), $(B EAX)
 	<dt>$(B BL), $(B BH), $(B BX), $(B EBX)
@@ -149,6 +157,30 @@
 	<dt>$(B XMM0), $(B XMM1), $(B XMM2), $(B XMM3),
 	    $(B XMM4), $(B XMM5), $(B XMM6), $(B XMM7)
 	</dl></dl>
+	
+<h3>x86-64</h3>
+	<dl><dl>
+	<dt>$(B All defined x86 registers, and):
+	<dt>$(B RAX), $(B RBX), $(B RCX), $(B RDX)
+	<dt>$(B BPL), $(B RBP)
+	<dt>$(B SPL), $(B RSP)
+	<dt>$(B DIL), $(B RDI)
+	<dt>$(B SIL), $(B RSI)
+	<dt>$(B R8L), $(B R8W), $(B R8D), $(B R8)
+	<dt>$(B R9L), $(B R9W), $(B R9D), $(B R9)
+	<dt>$(B R10L), $(B R10W), $(B R10D), $(B R10)
+	<dt>$(B R11L), $(B R11W), $(B R11D), $(B R11)
+	<dt>$(B R12L), $(B R12W), $(B R12D), $(B R12)
+	<dt>$(B R13L), $(B R13W), $(B R13D), $(B R13)
+	<dt>$(B R14L), $(B R14W), $(B R14D), $(B R14)
+	<dt>$(B R15L), $(B R15W), $(B R15D), $(B R15)
+	<dt>$(B CR8)
+	<dt>$(B XMM8), $(B XMM9), $(B XMM10), $(B XMM11),
+	    $(B XMM12), $(B XMM13), $(B XMM14), $(B XMM15)
+	</dl></dl>
+	
+	Also note that the sizes of certain registers (DR0-DR6, CR0-CR4, etc.) have
+	increased for the x86-64.
 
 <h3>Special Cases</h3>
 
@@ -280,19 +312,42 @@
     $(I Identifier) $(B .) $(I DotIdentifier)
 )
 
-	$(P The operand syntax more or less follows the Intel CPU documentation
-	conventions.
+<h3>x86 and x86-64</h3>
+
+	$(P For these platforms, the operand syntax more or less follows the Intel
+	CPU documentation conventions.
 	In particular, the convention is that for two operand instructions
 	the source is the right operand and the destination is the left
 	operand.
 	The syntax differs from that of Intel's in order to be compatible
 	with the D language tokenizer and to simplify parsing.
 	)
-
-	$(P The $(B seg) means load the segment number that the symbol is
-	in. This is not relevant for flat model code.
-	Instead, do a move from the relevant segment register.
+	
+	$(P Using $(B offsetof) will cause the operand to provide the address of a
+	label.
+	)
+	
+	$(P The $(B seg) keyword means load the segment number that the symbol is
+	in. This is not relevant for flat model code. Instead, do a move from the
+	relevant segment register.
 	)
+	
+--------------
+version(X86) asm
+{
+    mov EAX, EBX;             // Move the contents of EBX to EAX
+    cpuid;                    // Use the CPUID opcode
+    cmp EAX, 0;               // Compare EAX with 0
+    jz L1;                    // Jump to L1 if EAX is 0
+    mov EBX, offsetof L3;     // Move the address of L3 into EBX
+    mov x[EBP], EDX;          // Store EDX in the x variable
+    jmp L2;                   // Jump to L2
+L1: mov dword ptr [ESI+4], 0; // Store 4 bytes of 0 at the address in ESI + 4
+L2: mov ECX, 5;               // Move 5 to ECX
+L3: rep;                      // Repeat MOVSD 5 times
+    movsd;
+}
+--------------
 
 <h3>Operand Types</h3>
 
@@ -324,7 +379,12 @@
 add	int ptr [EAX],7		;
 --------------
 
-	$(P $(B far ptr) is not relevant for flat model code.
+	$(P A $(B byte ptr) would indicate a 1-byte operand size, a $(B short ptr)
+	or a $(B word ptr) would indicate a 2-byte operand size, an $(B int ptr),
+	$(B dword ptr) or $(B float ptr) would indicate 4 bytes, a $(B qword ptr),
+	or $(B double ptr) would indicate 8 bytes, and a $(B real ptr) would
+	indicate a 10-byte real number operand size. $(B far ptr) is not relevant
+	for flat model code; $(B near ptr) is implied as the default case.
 	)
 
 <h3>Struct/Union/Class Member Offsets</h3>
@@ -385,13 +445,13 @@
 
 	$(DT $(B __LOCAL_SIZE))
 	$(DD This gets replaced by the number of local bytes in the local
-	stack frame. It is most handy when the $(B naked) is invoked
+	stack frame. It is most handy when $(B naked) is invoked
 	and a custom stack frame is programmed.
 	)
 
 	)
 
-<h2>Opcodes Supported</h2>
+<h2>x86 and x86-64 Opcodes Supported</h2>
 
 	$(TABLE1
 	<tr>
@@ -1106,91 +1166,136 @@
 	</tr><tr>
 	<td>pmulhrw</td>
 	<td>pswapd</td>
+	<td></td>
+	<td></td>
+	<td></td>
 	</tr>
 	)
 
-$(COMMENT
-SSE4.1
-
-blendpd
-blendps
-blendvpd
-blendvps
-dppd
-dpps
-extractps
-insertps
-movntdqa
-mpsadbw
-packusdw
-pblendub
-pblendw
-pcmpeqq
-pextrb
-pextrd
-pextrq
-pextrw
-phminposuw
-pinsrb
-pinsrd
-pinsrq
-pmaxsb
-pmaxsd
-pmaxud
-pmaxuw
-pminsb
-pminsd
-pminud
-pminuw
-pmovsxbd
-pmovsxbq
-pmovsxbw
-pmovsxwd
-pmovsxwq
-pmovsxdq
-pmovzxbd
-pmovzxbq
-pmovzxbw
-pmovzxwd
-pmovzxwq
-pmovzxdq
-pmuldq
-pmulld
-ptest
-roundpd
-roundps
-roundsd
-roundss
-
-SSE4.2
-
-crc32
-pcmpestri
-pcmpestrm
-pcmpistri
-pcmpistrm
-pcmpgtq
-popcnt
-
-VMS
-
-invept
-invvpid
-vmcall
-vmclear
-vmlaunch
-vmresume
-vmptrld
-vmptrst
-vmread
-vmwrite
-vmxoff
-vmxon
-
-SMX
+<h3>SSE4.1 Opcodes Supported</h3>
+	
+	$(TABLE1
+	<tr>
+	<td>blendpd</td>
+	<td>blendps</td>
+	<td>blendvpd</td>
+	<td>blendvps</td>
+	<td>dppd</td>
+	</tr><tr>
+	<td>dpps</td>
+	<td>insertps</td>
+	<td>movntdqa</td>
+	<td>mpsadbw</td>
+	<td>packusdw</td>
+	</tr><tr>
+	<td>pblendub</td>
+	<td>pblendw</td>
+	<td>pcmpeqq</td>
+	<td>pextrd</td>
+	<td>pextrq</td>
+	</tr><tr>
+	<td>pextrw</td>
+	<td>phminposuw</td>
+	<td>pinsrb</td>
+	<td>pinsrd</td>
+	<td>pinsrq</td>
+	</tr><tr>
+	<td>pmaxsb</td>
+	<td>pmaxsd</td>
+	<td>pmaxud</td>
+	<td>pmaxuw</td>
+	<td>pminsb</td>
+	</tr><tr>
+	<td>pminsd</td>
+	<td>pminud</td>
+	<td>pminuw</td>
+	<td>pmovsxbd</td>
+	<td>pmovsxbq</td>
+	</tr><tr>
+	<td>pmovsxbw</td>
+	<td>pmovsxdq</td>
+	<td>pmovsxwd</td>
+	<td>pmovsxwq</td>
+	<td>pmovzxbd</td>
+	</tr><tr>
+	<td>pmovzxbq</td>
+	<td>pmovzxbw</td>
+	<td>pmovzxdq</td>
+	<td>pmovzxwd</td>
+	<td>pmovzxwq</td>
+	</tr><tr>
+	<td>pmuldq</td>
+	<td>pmulld</td>
+	<td>ptest</td>
+	<td>roundpd</td>
+	<td>roundps</td>
+	</tr><tr>
+	<td>roundsd</td>
+	<td>roundss</td>
+	<td></td>
+	<td></td>
+	<td></td>
+	</tr>
+	)
+	
+<h3>SSE4.2 Opcodes Supported</h3>
+	
+	$(TABLE1
+	<tr>
+	<td>crc32</td>
+	<td>pcmpestri</td>
+	<td>pcmpestrm</td>
+	<td>pcmpistri</td>
+	<td>pcmpistrm</td>
+	</tr><tr>
+	<td>pcmpgtq</td>
+	<td>popcnt</td>
+	<td></td>
+	<td></td>
+	<td></td>
+	</tr>
+	)
+	
+<h3>VMS Opcodes Supported</h3>
+	
+	$(TABLE1
+	<tr>
+	<td>invept</td>
+	<td>invvpid</td>
+	<td>vmcall</td>
+	<td>vmclear</td>
+	<td>vmlaunch</td>
+	</tr><tr>
+	<td>vmresume</td>
+	<td>vmptrld</td>
+	<td>vmptrst</td>
+	<td>vmread</td>
+	<td>vmwrite</td>
+	</tr><tr>
+	<td>vmxoff</td>
+	<td>vmxon</td>
+	<td></td>
+	<td></td>
+	<td></td>
+	</tr>
+	)
+	
+<h3>SMX Opcodes Supported</h3>
+	
+	$(TABLE1
+	<tr>
+	<td>getsec</td>
+	</tr>
+	)
+	
+<h2>Additional Opcodes</h2>
 
-getsec
-)
+	$(P Additional opcodes supported by new or different processors and
+	that are not listed here may be implemented by a D implementation, provided
+	that they maintain the standard grammar and syntax outlined in this
+	document. However, it would be appreciated if the issue of missing or new
+	opcodes are raised through an enhancement request with Bugzilla.
+	)
 
 )
 
